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1 MX25R1035F wide vcc range, 1m-bit [x 1/x 2/x 4] cmos mxsmio ? (serial multi i/o) flash memory key features ? wide range 1.7 to 3.6 volt for read, erase, and program operations ? multi i/o support - single i/o, dual i/o and quad i/o ? program suspend/resume & erase suspend/resume ? low power mode and high performance mode advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
2 contents 1. features .............................................................................................................................................................. 4 2. general description ..................................................................................................................................... 6 table 1. additional feature ............................................................................................. ............................. 7 3. pin configurations ......................................................................................................................................... 8 4. pin description .................................................................................................................................................. 8 5. block diagram ................................................................................................................................................... 9 6. dat a protection .............................................................................................................................................. 10 table 2. protected area sizes ................................................................................................................... 11 t able 3. 8k-bit secured otp defnition .................................................................................................... 12 7. memor y organization ................................................................................................................................... 13 table 4. memory organization ............................................................................................ ...................... 13 8. device operation ............................................................................................................................................ 14 9. command description ................................................................................................................................... 16 table 5. command set ............................................................................................. ................................. 16 9-1. write enable (wren) .............................................................................................................................. 19 9-2. write disable (wrdi) ............................................................................................................................... 20 9-3. read identifcation (rdid) ....................................................................................................................... 21 9-4. read electronic signature (res) ............................................................................................................ 22 9-5. read electronic manufacturer id & device id (rems) ........................................................................... 23 9-6. id read .................................................................................................................................................... 24 table 6. id defnitions ............................................................................................ .................................. 24 9-7. read status register (rdsr) ................................................................................................................. 25 9-8. read confguration register (rdcr) ...................................................................................................... 30 9-9. write status register (wrsr) ................................................................................................................. 31 t able 7. protection modes ............................................................................................. ............................ 32 9-10. read data bytes (read) ........................................................................................................................ 35 9-11. read data bytes at higher speed (fast_read) .................................................................................. 36 9-12. dual read mode (dread) ...................................................................................................................... 37 9-13. 2 x i/o read mode (2read) ................................................................................................................... 38 9-14. quad read mode (qread) .................................................................................................................... 39 9-15. 4 x i/o read mode (4read) ................................................................................................................... 40 9-16. burst read ............................................................................................................................................... 42 9-17. performance enhance mode ................................................................................................................... 43 9-18. performance enhance mode reset ......................................................................................................... 45 9-19. sector erase (se) .................................................................................................................................... 46 9-20. block erase (be32k) ............................................................................................................................... 47 9-21. block erase (be) ..................................................................................................................................... 48 9-22. chip erase (ce) ....................................................................................................................................... 49 9-23. page program (pp) ................................................................................................................................. 50 9-24. 4 x i/o page program (4pp) .................................................................................................................... 52 9-25. deep power-down (dp) ........................................................................................................................... 53 9-26. enter secured otp (enso) .................................................................................................................... 54 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
3 9-27. exit secured otp (exso) ....................................................................................................................... 54 9-28. read security register (rdscur) ......................................................................................................... 54 table 8. security register defnition ............................................................................................ ............. 55 9-29. write security register (wrscur) ......................................................................................................... 55 9-30. program/erase suspend/resume ........................................................................................................... 56 t able 9. readable area of memory while a program or erase operation is suspended ......................... 56 table 10. acceptable commands during program/erase suspend after tpsl/tesl ................................ 56 t able 11. acceptable commands during suspend (tpsl/tesl not required) ........................................... 57 9-31. program resume and erase resume ..................................................................................................... 58 9-32. no operation (nop) ................................................................................................................................ 59 9-33. software reset (reset-enable (rsten) and reset (rst)) ................................................................... 59 9-34. high voltage operation ............................................................................................................................ 60 9-35. read sfdp mode (rdsfdp) .................................................................................................................. 61 t able 12. signature and parameter identifcation data values ................................................................ 62 t able 13. parameter table (0): jedec flash parameter tables .............................................................. 63 t able 14. parameter table (1): macronix flash parameter tables ........................................................... 65 10. reset.................................................................................................................................................................. 67 t able 15-1. reset timing-(power on) ............................................................................................ ........... 67 table 15-2. reset timing-(other operation) ............................................................................................ . 67 11. power-on state ............................................................................................................................................. 68 12. electrical specifications ........................................................................................................................ 69 table 16. absolute maximum ratings ....................................................................................................... 69 t able 17. capacitance ............................................................................................. .................................. 69 table 18. dc characteristics ............................................................................................. ........................ 71 table 19. ac characteristics .................................................................................................................... 73 13. opera ting conditions ................................................................................................................................. 77 table 20. power-up/down v oltage and timing ......................................................................................... 79 13-1. initial delivery state ................................................................................................................................. 79 14. erase and programming performance .............................................................................................. 80 15. latch-up characteristics ........................................................................................................................ 81 16. ordering information ................................................................................................................................ 82 17. part name description ............................................................................................................................... 83 18. package informa tion .................................................................................................................................. 84 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
4 1. features wide vcc range 1m-bit [x 1/x 2/x 4] cmos mxsmio ? (serial multi i/o) flash memory general ? supports serial peripheral interface -- mode 0 and mode 3 ? 1,048,576 x 1 bit structure or 524,288 x 2 bits (two i/o mode) structure or 262,144 x 4 bits (four i/o mode) structure ? equal sectors with 4k byte each, or equal blocks with 32k/64k byte each - any block can be erased individually ? single power supply operation - 1.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v performance ? high performance - fast read - 1 i/o: 80mhz with 8 dummy cycles - 2 i/o: 80mhz with 4 dummy cycles, equivalent to 160mhz - 4 i/o: 80mhz with 2+4 dummy cycles, equivalent to 320mhz - fast program and erase time - 8/16/32/64 byte wrap-around burst read mode ? low power consumption ? typical 100,000 erase/program cycles ? 20 years data retention software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defnes the size of the area to be software protection against program and erase instructions ? additional 8k bits secured otp - features unique identifer. - factory locked identifable and customer lockable ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector or block - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) ? status register feature ? command reset ? program/erase suspend and program/erase resume ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems command for 1-byte manufacturer id and 1-byte device id ? support serial flash discoverable parameters (sfdp) mode advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
5 hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? reset#/sio3 - hardware reset pin or serial input & output for 4 x i/o read mode ? package - 8-pin sop (150mil/200mil) - 8-land uson (2x3mm) - all devices are rohs compliant and halogen-free advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
6 2. general description MX25R1035F is 1mb bits serial flash memory, which is confgured as 131,072 x 8 internally. when it is in four i/o mode, the structure becomes 262,144 bits x 4 or 524,288 bits x 2. MX25R1035F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single i/o mode. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. when it is in four i/o read mode, the si pin, so pin, wp# pin and reset# pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data output. the MX25R1035F mxsmio ? (serial multi i/o) provides sequential read operation on the whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the specifed page or sector/block locations will be executed. progr am command is executed on byte basis, or page (256 bytes) basis, or word basis. erase command is executed on 4k-byte sector, 32k-byte block, or 64k-byte block, or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. the MX25R1035F utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
7 table 1. additional feature protection and security MX25R1035F flexible block protection (bp0-bp3) v 8k-bit security otp v fast read performance low power mode (confguration register-2 bit1= 0) high performance mode (confguration register-2 bit1= 1) i/o 1 i/o 1i/2o 2 i/o 1i/4o 4 i/o 1 i/o 1i/2o 2 i/o 1i/4o 4 i/o dummy cycle 8 8 4 8 6 8 8 4 8 6 frequency 33mhz 16mhz 16mhz 16mhz 16mhz 80mhz 80mhz 80mhz 80mhz 80mhz advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
8 3. pin configurations 4. pin description symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 4xi/o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 4xi/o read mode) sclk clock input wp#/sio2 write protection active low or serial data input & output (for 4xi/o read mode) reset#/sio3 hardware reset pin active low or serial data input & output (for 4xi/o read mode) vcc + 1.7v ~ 3.6v power supply gnd ground 8-land uson (2x3mm) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc reset#/sio3 sclk si/sio0 8-pin sop (150mil/200mil) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc reset#/sio3 sclk si/sio0 8 7 6 5 note: 1. reset# and wp# with internal pull high circuit. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
9 5. block diagram address generator memory array y-decoder x-decoder data register sram buffer si/sio0 so/sio1 sio2 * sio3 * wp# * reset# * cs# sclk clock generator state machine mode logic sense amplifier hv generator output buffer * depends on part number options. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
10 6. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may protect the flash. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before issuing other commands to change data. ? deep power down mode: by entering deep power down mode, the fash device is under protected from writing all commands except toggling the cs#. for more detail please see "9-25. deep power-down (dp)" . ? advanced security features: there are some protection and security features which protect content from inadvertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area defnition is shown as "table 2. protected area sizes" , the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. - the hardware proteced mode (hpm) use wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and status register write protect (srwd) bit. if the system goes into four i/o mode, the feature of hpm will be disabled. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
11 table 2. protected area sizes protected area sizes (tb bit = 0) status bit protect level bp3 bp2 bp1 bp0 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 1st) 0 0 1 0 2 (2blocks, block 0th-1st) 0 0 1 1 3 (2blocks, protect all) 0 1 0 0 4 (2blocks, protect all) 0 1 0 1 5 (2blocks, protect all) 0 1 1 0 6 (2blocks, protect all) 0 1 1 1 7 (2blocks, protect all) 1 0 0 0 8 (2blocks, protect all) 1 0 0 1 9 (2blocks, protect all) 1 0 1 0 10 (2blocks, protect all) 1 0 1 1 11 (2blocks, protect all) 1 1 0 0 12 (2blocks, protect all) 1 1 0 1 13 (2blocks, protect all) 1 1 1 0 14 (2blocks, protect all) 1 1 1 1 15 (2blocks, protect all) protected area sizes (tb bit = 1) status bit protect level bp3 bp2 bp1 bp0 0 0 0 0 0 (none) 0 0 0 1 1 (1block, block 0th) 0 0 1 0 2 (2blocks, block 0th-1st) 0 0 1 1 3 (2blocks, protect all) 0 1 0 0 4 (2blocks, protect all) 0 1 0 1 5 (2blocks, protect all) 0 1 1 0 6 (2blocks, protect all) 0 1 1 1 7 (2blocks, protect all) 1 0 0 0 8 (2blocks, protect all) 1 0 0 1 9 (2blocks, protect all) 1 0 1 0 10 (2blocks, protect all) 1 0 1 1 11 (2blocks, protect all) 1 1 0 0 12 (2blocks, protect all) 1 1 0 1 13 (2blocks, protect all) 1 1 1 0 14 (2blocks, protect all) 1 1 1 1 15 (2blocks, protect all) note: the device is ready to accept a chip erase instruction if, and only if, all block protect (bp3, bp2, bp1, bp0) are 0. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
12 ii. additional 8k-bit secured otp for unique identifer: to provide 8k-bit one-time program area for setting device unique serial number - which may be set by factory or system maker. the 8k-bit secured otp area is composed of two rows of 4k-bit. customer could lock the frst 4k-bit otp area and factory could lock the other . - security register bit 0 indicates whether the 2 nd 4k-bit is locked by factory or not. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "table 8. security register defnition" for security register bit defnition and table of "table 3. 8k-bit secured otp defnition" for address range defnition. - to program 8k-bit secure d otp by entering secured otp mode (with enso command), and going through normal program procedure, and then exiting secured otp mode by writing exso command. note: once lock-down whatever by factory or customer, the corresponding secured area cannot be changed any more. while in 8k-bit secured otp mode, array access is not allowed. table 3. .elw6hfxuhg273hqlwlrq address range size lock-down xxx000~xxx1ff 4096-bit determined by customer xxx200~xxx3ff 4096-bit determined by factory advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
13 table 4. memory organization 7. memory organization block sector address range 1 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
14 8. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. when incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next cs# falling edge. in standby mode, so pin of the device is high-z. 3. when correct command is inputted to this device, it enters active mode and remains in active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock (sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as "figure 1. serial modes supported" . 5. for the following instructions: rdid, rdsr, rdcr, rdscur, read, fast_read, dread, 2read, 4read, qread, rdsfdp, res, rems, the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be32k, be, ce, pp, 4pp, dp, enso, exso, wrscur, suspend, resume, nop, rsten, rst, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. while a write status register , program or erase operation is in progress, access to the memory array is neglected and will not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
15 figure 2. serial input timing figure 3. output timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
16 9. command description table 5. command set read/write array commands i/o 1 1 2 2 4 4 command (byte) read (normal read) fast read (fast read data) 2read (2 x i/o read command) dread (1i / 2o read command) 4read (4 x i/o read) qread (1i/4o read) 1st byte 03 (hex) 0b (hex) bb (hex) 3b (hex) eb (hex) 6b (hex) 2nd byte add1 add1 add1 add1 add1 add1 3rd byte add2 add2 add2 add2 add2 add2 4th byte add3 add3 add3 add3 add3 add3 5th byte dummy dummy dummy dummy dummy action n bytes read out until cs# goes high n bytes read out until cs# goes high n bytes read out by 2 x i/o until cs# goes high n bytes read out by dual output until cs# goes high quad i/o read with 6 dummy cycles n bytes read out by quad output until cs# goes high i/o 1 4 1 1 1 1 1 command (byte) pp (page program) 4pp (quad page program) se (sector erase) be 32k (block erase 32kb) be (block erase 64kb) ce (chip erase) rdsfdp (read sfdp) 1st byte 02 (hex) 38 (hex) 20 (hex) 52 (hex) d8 (hex) 60 or c7 (hex) 5a (hex) 2nd byte add1 add1 add1 add1 add1 add1 3rd byte add2 add2 add2 add2 add2 add2 4th byte add3 add3 add3 add3 add3 add3 5th byte dummy action to program the selected page quad input to program the selected page to erase the selected sector to erase the selected 32kb block to erase the selected block to erase whole chip read sfdp mode advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
17 register/setting commands command (byte) wren (write enable) wrdi (write disable) rdsr (read status register) rdcr (read confguration register) wrsr (write status register) pgm/ers suspend (suspends program/erase) 1st byte 06 (hex) 04 (hex) 05 (hex) 15 (hex) 01 (hex) 75 or b0 (hex) 2nd byte values 3rd byte values 4th byte values 5th byte action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to read out the values of the status register to read out the values of the confguration register -1 & confguration register -2 to write new values of the confguration/ status register program/erase operation is interrupted by suspend command command (byte) pgm/ers resume (resumes program/erase) dp (deep power down) sbl (set burst length) 1st byte 7a or 30 (hex) b9 (hex) c0 (hex) 2nd byte value 3rd byte 4th byte 5th byte action to continue performing the suspended program/erase sequence enters deep power down mode to set burst length advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
18 command (byte) rdid (read identifc- ation) res (read electronic id) rems (read electronic manufacturer & device id) enso (enter secured otp) exso (exit secured otp) rdscur (read security register) wrscur (write security register) 1st byte 9f (hex) ab (hex) 90 (hex) b1 (hex) c1 (hex) 2b (hex) 2f (hex) 2nd byte x x 3rd byte x x 4th byte x add (note 2) 5th byte action outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out 1-byte device id output the manufacturer id & device id to enter the 8k-bit secured otp mode to exit the 8k-bit secured otp mode to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be update) command (byte) nop (no operation) rsten (reset enable) rst (reset memory) release read enhanced 1st byte 00 (hex) 66 (hex) 99 (hex) ff (hex) 2nd byte 3rd byte 4th byte 5th byte action (note 3) all these commands ffh, 00h, aah or 55h will escape the performance mode id/reset commands note 1: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 2: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hid - den mode. note 3: before executing rst command, rsten command must be executed. if there is any other command to interfere, the reset operation will be disabled. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
19 9-1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, se, be32k, be, ce, and wrsr, which are intended to change the device content wel bit should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes lowsending wren instruction code cs# goes high. the sio[3:1] are "don't care" . figure 4. write enable (wren) sequence 21 34567 high-z 0 06h command sclk si cs# so mode 3 mode 0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
20 9-2. write disable (wrdi) the write disable (wrdi) instruction is to reset w rite enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. the sio[3:1] are "don't care". the wel bit is reset by following situations: - power-up - reset# pin driven low - completion of write disable (wrdi) instruction - completion of write status register (wrsr) instruction - completion of page program (pp) instruction - completion of quad page program (4pp) instruction - completion of sector erase (se) instruction - completion of block erase 32kb (be32k) instruction - completion of block erase (be) instruction - completion of chip erase (ce) instruction - program/erase suspend - completion of softreset command - completion of write security register (wrscur) command figure 5. write disable (wrdi) sequence 21 34567 high-z 0 mode 3 mode 0 04h command sclk si cs# so advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
21 9-3. read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the macronix manufacturer id and device id are listed as "table 6. id defnitions" . 7kh vhtxhqfhrilvvxlqj5','lqvwuxfwlrqlv&6jrhvor:vhqlqj5','lqvwuxfwlrqfrh:elwv,'dwdrxw rq62:wrhq5','rshudwlrqfdqulyh&6wrkljkdwdqwlphxulqjdwdrxw while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on wkhffohrisurjudphudvhrshudwlrqklfklvfxuuhqwolqsurjuhvv:khq&6jrhvkljkwkhhylfhlvdwvwdqe stage. figure 6. read identifcation (rdid) sequence 21 345678 9 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9fh mode 3 mode 0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
22 9-4. read electronic signature (res) res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as "table 6. id defnitions" . this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. the sio[3:1] are "don't care". the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeatedly if continuously send the additional clock cycles on sclk while cs# is at low . figure 7. read electronic signature (res) sequence 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb msb t res2 sclk cs# si so abh command mode 3 mode 0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
23 9-5. read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for macronix (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst. the device id values are listed in "table 6. id defnitions" . if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. figure 8. read electronic manufacturer & device id (rems) sequence 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so 90h high-z command mode 3 mode 0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
24 9-6. id read user can execute this id read instruction to identify the device id and manufacturer id. the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code24-bits id data out on so to end rdid operation can drive cs# to high at any time during data out. after the command cycle, the device will immediately output data on the falling edge of sclk. the manufacturer id, memory type, and device id data byte will be output continuously , until the cs# goes high. while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. table 6. id defnitions command type command MX25R1035F rdid 9fh manufactory id memory type memory density c2 28 11 res abh electronic id 11 rems 90h manufactory id device id c2 11 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
25 9-7. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. the sio[3:1] are "don't care". figure 9. read status register (rdsr) sequence 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05h mode 3 mode 0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
26 wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command read array data (same add ress of pgm/ers) program /er ase su ccessfully yes yes program /erase fail no start verify ok? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no * issue rdsr to check bp[3:0]. rdsr command read w el=0, bp[3:0] , q e, and srwd data figure 10. program/erase fow with read array data for user to check if program/erase operation is fnished or not, rdsr instruction fow are shown as follows: advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
27 figure 11. program/erase fow without read array data (read p_fail/e_fail fag) wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command rdscur command program /er ase su ccessfully yes no program /erase fail yes start p_fail/e_fail =1 ? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel =1? no * issue rdsr to check bp[3:0]. rdsr command read w el=0, bp[3:0] , q e, and srwd data advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
28 status register note 1: see the "table 2. protected area sizes" . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit status register the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is applied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrmed as 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in "table 2. protected area sizes" ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be/be32k) and chip erase (ce) instructions (only if block protect bits (bp3:bp0) set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default, which is un-protected. qe bit. the quad enable (qe) bit, non-volatile bit, while it is "0" (factory default), it performs non-quad and wp#, reset# are enable. while qe is "1", it performs quad i/o mode and wp#, reset# are disabled. in the other word, if the system goes into four i/o mode (qe=1), the feature of hpm and reset will be disabled. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. the srwd bit defaults to be "0". advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
29 confguration register the confguration register is able to change the default status of flash memory. flash memory will be confgured after the cr bit is set. tb bit the top/bottom (tb) bit is a non-volatile otp bit. the top/bottom (tb) bit is used to confgure the block protect area by bp bit (bp3, bp2, bp1, bp0), starting from top or bottom of the memory array. the tb bit is defaulted as 0, which means top area protect. when it is set as 1, the protect area will change to bottom area of the memory device. to write the tb bit requires the write status register (wrsr) instruction to be executed. l/h switch bit the low power / high performance bit is a volatile bit. user can change the value of l/h switch bit to keep low power mode or high performance mode. the default value of the l/h switch bit is "0" after power on or reset, which means that the device is at low power mode. confguration register - 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved reserved reserved reserved tb (top/bottom selected) reserved reserved reserved x x x x 0=top area protect 1=bottom area protect (default=0) x x x x x x x otp x x x confguration register - 2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved reserved reserved reserved reserved reserved l/h switch reserved x x x x x x 0 = low power mode (default) 1 = high performance mode x x x x x x x volatile bit x advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
30 9-8. read confguration register (rdcr) the rdcr instruction is for reading confguration register bits. the read confguration register can be read at any time (even in program/erase/write confguration register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write confguration register operation is in progress. the sequence of issuing rdcr instruction is: cs# goes low sending rdcr instruction code confguration register data out on so. the sio[3:1] are don't care. figure 12. read confguration register (rdcr) sequence 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 configuration register-1 out high-z msb 7 6543210 configuration register-2 out msb 7 sclk si cs# so 15h mode 3 mode 0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
31 9-9. write status register (wrsr) the wrsr instruction is for changing the values of status register bits and confguration register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the protected area of memory (as shown in "table 2. protected area sizes" ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on sics# goes high. the cs# must go high exactly at the 8 bits, 16 bits or 24 bits data boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. please note that there is another parameter, "write status register cycle time for mode changing switching (twms)", which is only for the self-timed of mode switching. for more detail please check "table 19. ac characteristics" . figure 13. write status register (wrsr) sequence 21 345678 9 10 11 12 13 14 15 status register in configuration register -1 in 0 msb sclk si cs# so 01h high-z command mode 3 mode 0 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 24 25 26 27 28 29 30 31 configuration register -2 in 23 22 21 20 19 18 17 16 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
32 software protected mode (spm): - when srwd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm) note: if srwd bit=1 but wp#/sio2 is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/sio2 to against data modifcation. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. table 7. protection modes note: 1. as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in "table 2. protected area sizes" . mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
33 figure 14. wrsr fow wr en co mm and wr sr co mm and write status register data rdsr command wrsr successfully yes yes wrsr fail no start verify ok? wip=0? no rds r command yes wel=1? no rds r command read w el=0, bp[3:0] , q e, and srwd data advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
34 figure 15. wp# setup timing and hold timing during wrsr when srwd=1 high-z 01h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so note: wp# must be kept high until the embedded operation fnish. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
35 9-10. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes lowsending read instruction code 3-byte address on si data out on soto end read operation can use cs# to high at any time during data out. figure 16. read data bytes (read) sequence sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 0 msb msb 2 39 data out 2 03h high-z command mode 3 mode 0 24-bit address advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
36 9-11. read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si1-dummy byte (default) address on si data out on so to end fast_read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 17. read at higher speed (fast_read) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0bh command mode 3 mode 0 24-bit address advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
37 9-12. dual read mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruction. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruction, the following data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing dread instruction is: cs# goes low sending dread instruction 3-byte address on si 8-bit dummy cycle data out interleave on sio1 & sio0 to end dread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. figure 18. dual read mode sequence (command 3b) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 30 31 32 39 40 41 43 44 45 42 3b d4 d5 d2 d3 d7 d6 d6 d4 d0 d7 d5 d1 command 24 add cycle 8 dummy cycle a23 a22 a1 a0 data out 1 data out 2 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
38 9-13. 2 x i/o read mode (2read) the 2read instruction enables double t ransfer rate of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address interleave on sio1 & sio0 4-bit dummy cycle on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 19. 2 x i/o read mode sequence (command bb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 18 19 20 bb(hex) 21 22 23 24 25 26 27 28 29 p0 p2 p1 p3 d4 d5 d2 d3 d7 d6 d6 d4 d0 d7 d5 d1 command 12 add cycle 4 dummy cycle a22 a20 a2 a0 a3 a1 a23 a21 data out 1 data out 2 note: si/sio0 or so/sio1 should be kept "0h" or "fh" in the frst two dummy cycles. in other words, p2=p0 or p3=p1 is necessary. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
39 9-14. quad read mode (qread) the qread instruction enable quad throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single qread instruction. the address counter rolls over to 0 when the highest address has been reached. once writing qread instruction, the following data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing qread instruction is: cs# goes low sending qread instruction 3-byte address on si 8-bit dummy cycle data out interleave on sio3, sio2, sio1 & sio0 to end qread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, qread instruction is rejected without any impact on the program/erase/write status register current cycle. figure 20. quad read mode sequence (command 6b) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 29 9 30 31 32 33 38 39 40 41 42 6b high impedance sio2 high impedance sio3 8 dummy cycles d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d5 d6 d7 a23 a22 a2 a1 a0 command 24 add cycles data out 1 data out 2 data out 3 ? ? ? advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
40 9-15. 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. another sequence of issuing 4read instruction especially useful in random access is: cs# goes low sending 4read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out still cs# goes high cs# goes low (reduce 4 read instruction) 24-bit random access address. in the performance-enhancing mode, p[7:4] must be toggling with p[3:0]; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh, 00h, aah or 55h and afterwards cs# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
41 figure 21. 4 x i/o read mode sequence 21 345678 0 sclk sio0 sio1 sio2 sio3 cs# 9 1210 11 13 14 ebh p4 p0 p5 p1 p6 p2 p7 p3 15 16 17 18 19 20 21 22 23 24 command 4 dummy cycles performance enhance indicator (note) mode 3 mode 0 6 add cycles a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 d4 d0 d5 d1 data out 1 data out 2 data out 3 d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 mode 3 mode 0 note: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) is inhibited. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
42 9-16. burst read this device supports burst read. to set the burst length, following command operation is required issuing command: c0h in the frst byte (8-clocks), following 4 clocks defning wrap around enable with 0h and disable with1h. next 4 clocks is to defne wrap around depth. defnition as following table: the wrap around unit is defned within the 256byte page, with random initial address. its defned as wrap-around mode disable for the default state of the device. to exit wrap around, it is required to issue another c0 command in which data=1xh. otherwise, wrap around status will be retained until power down or reset command. to change wrap around depth, it is requried to issue another c0 command in which data=0xh. ebh supports wrap around feature after wrap around enable. the device id default without burst read. data wrap around wrap depth 00h yes 8-byte 01h yes 16-byte 02h yes 32-byte 03h yes 64-byte 1xh no x 0 cs# sclk sio c0h d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 6 7 8 9 10 1 12 13 14 15 5 mode 3 mode 0 figure 22. burst read advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
43 9-17. performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. ebh command supports enhance mode. the performance enhance mode is not supported in dual i/o mode. after entering enhance mode, following cs# go high, the device will stay in the read mode and treat cs# go low of the frst clock as address instead of command cycle. to exit enhance mode, a new fast read command whose frst two dummy cycles is not toggle then exit. or issue ffh command to exit enhance mode. performance enhance mode is only available on high performance mode. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
44 figure 23. 4 x i/o read enhance performance mode sequence 21 345678 0 sclk sio0 sio1 cs# 9 1210 11 13 14 ebh 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 n sio2 sio3 sio0 sio1 sio2 sio3 performance enhance indicator (note) sclk cs# performance enhance indicator (note) mode 3 mode 0 a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 p4 p0 p5 p1 p6 p2 p7 p3 a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 p4 p0 p5 p1 p6 p2 p7 p3 command 4 dummy cycles 4 dummy cycles 6 add cycles 6 add cycles d4 d0 d5 d1 data out 1 data out 2 data out n d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 d4 d0 d5 d1 data out 1 data out 2 data out n d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 mode 3 mode 0 note: 1. performance enhance mode, if p7p3 & p6p2 & p5p1 & p4p0 (toggling), ex: a5, 5a, 0f, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. 2. reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
45 9-18. performance enhance mode reset to conduct the performance enhance mode reset operation, ffh command code, 8 clocks, should be issued in 1 i/o sequence. if the system controller is being reset during operation, the fash device will return to the standard 1 i/o operation. the sio[3:1] are "don't care". figure 24. performance enhance mode reset for fast read quad i/o 21 34567 mode 3 don?t care don?t care don?t care mode mode 3 mode sclk sio0 cs# sio1 ffh sio2 sio3 mode bit reset for quad i/o advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
46 figure 25. sector erase (se) sequence 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20h command mode 3 mode 0 24-bit address 9-19. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see "table 4. memory organization" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. the sio[3:1] are "don't care". the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the sector is protected by bp3, bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the sector. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
47 9-20. block erase (be32k) the block erase (be32k) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the block erase (be32k). any address of the block (see "table 4. memory organization" ) is a valid address for block erase (be32k) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte has been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be32k instruction is: cs# goes low sending be32k instruction code 3-byte address on si cs# goes high. the sio[3:1] are don't care. the self-timed block erase cycle time (tbe32k) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the sector erase cycle is in progress. the wip sets during the tbe32k timing, and clears when sector erase cycle is completed, and the write enable latch (wel) bit is cleared. if the block is protected by bp3~0, the array data will be protected (no change) and the wel bit still be reset. figure 26. block erase 32kb (be32k) sequence (command 52) 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52h command advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
48 9-21. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (please refer to "table 4. memory organization" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. the sio[3:1] are "don't care". the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the block erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the block. figure 27. block erase (be) sequence 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8h command mode 3 mode 0 24-bit address advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
49 9-22. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a w rite enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes lowsending ce instruction codecs# goes high. the sio[3:1] are "don't care". the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3, bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3, bp2, bp1, bp0 all set to "0". figure 28. chip erase (ce) sequence 21 34567 0 60h or c7h sclk si cs# command mode 3 mode 0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
50 9-23. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. the cs# must be kept low during the whole page program cycle; the cs# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed. the sio[3:1] are "don't care". advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
51 figure 29. page program (pp) sequence 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02h command mode 3 mode 0 24-bit address advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
52 9-24. 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3 as address and data input, which can improve programmer performance and the effectiveness of application. the 4pp operation frequency supports as fast as f4pp. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0]cs# goes high. figure 30. 4 x i/o page program (4pp) sequence a20 a21 a17 a16 a12 a8 a4 a0 a13 a9 a5 a1 d4 d0 d5 d1 21 3456789 6 add cycles data byte 1 data byte 2 data byte 3 data byte 4 0 a22 a18 a14 a10 a6 a2 a23 a19 a15 a11 a7 a3 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 sclk cs# sio0 sio1 sio3 sio2 38h command 10 11 12 13 14 15 16 17 18 19 20 21 mode 3 mode 0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
53 9-25. deep power-down (dp) the deep power-down (dp) instruction is for setting the device to minimum power consumption (the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, the device is in deep power-down mode, not standby mode. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction codecs# goes high. the sio[3:1] are "don't care". once the dp instruction is set, all instructions will be ignored except cs# toggling for trdp timing as "figure 32. release from deep power-down (rdp) sequence" . when power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for dp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not be executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode. in addition, a deep power down delay time (tdpdd) is required before release from deep power down once entering deep power down mode. figure 31. deep power-down (dp) sequence 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9h command mode 3 mode 0 figure 32. release from deep power-down (rdp) sequence stand-by mode deep power-down mode high-z cs# so/si trdp tcrdp advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
54 9-26. enter secured otp (enso) the enso instruction is for entering the additional 8k-bit secured otp mode. while the device is in 8k-bit secured otp mode, array access is not available. the additional 8k-bit secured otp is independent from main array, and may be used to store unique serial number for system identifer. after entering the secured otp mode, follow standard read or program procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. the sio[3:1] are "don't care". please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once security otp is lock down, only read related commands are valid. 9-27. exit secured otp (exso) the exso instruction is for exiting the additional 8k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. the sio[3:1] are "don't care". 9-28. read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously . the sequence of issuing rdscur instruction is : cs# goes lowsending rdscur instructionsecurity register data out on so cs# goes high. the sio[3:1] are "don't care". the defnition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for customer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 1 st 4k-bit secured otp area cannot be updated any more. program suspend status bit. program suspend bit (psb) indicates the status of program suspend operation. users may use psb to identify the state of fash memory. after the fash memory is suspended by program suspend command, psb is set to "1". psb is cleared to "0" after program operation resumes. erase suspend status bit. erase suspend bit (esb) indicates the status of erase suspend operation. users may use esb to identify the state of fash memory. after the fash memory is suspended by erase suspend command, esb is set to "1". esb is cleared to "0" after erase operation resumes. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
55 9-29. write security register (wrscur) the wrscur instruction is for changing the values of security register bits. the wren (w rite enable) instruction is required before issuing wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 1 st 4k-bit secured otp area. once the ldso bit is set to "1", the 1 st 4k-bit secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. the sio[3:1] are "don't care". the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. table 8. security register defnition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e_fail p_fail reserved esb (erase suspend status) psb (program suspend status) ldso (lock-down 1 st 4k-bit secured otp) secured otp indicator bit (2 nd 4k-bit secured otp) reserved 0=normal erase succeed 1=indicate erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) reserved 0=erase is not suspended 1=erase is suspended (default=0) 0=program is not suspended 1=program is suspended (default=0) 0 = not lockdown 1 = lock-down (cannot program/ erase otp) 0 = nonfactory lock 1 = factory lock non-volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit reserved read only read only read only read only otp read only program fail flag bit. while a program failure happened, the program fail flag bit would be set. if the program operation fails on a protected memory region, this bit will also be set. this bit can be the failure indication of one or more program operations. this fail fag bit will be cleared automatically after the next successful program operation. erase fail flag bit. while an erase failure happened, the erase fail flag bit would be set. if the erase operation fails on a protected memory region, this bit will also be set. this bit can be the failure indication of one or more erase operations. this fail fag bit will be cleared automatically after the next successful erase operation. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
56 9-30. program/erase suspend/resume the suspend instruction interrupts a page program, sector erase, or block erase operation to allow access to the memory array. after the program or erase operation has entered the suspended state, the memory array can be read except for the page being programmed or the sector or block being erased ( "table 9. readable area of memory while a program or erase operation is suspended" ). table 9. readable area of memory while a program or erase operation is suspended suspended operation readable region of memory array page program all but the page being programmed sector erase (4kb) all but the 4kb sector being erased block erase (32kb) all but the 32kb block being erased block erase (64kb) all but the 64kb block being erased when the serial fash receives the suspend instruction, there is a latency of tpsl or tesl ( "figure 33. suspend to read/program latency" ) before the write enable latch (wel) bit clears to 0 and the psb or esb sets to 1, after which the device is ready to accept one of the commands listed in "table 10. acceptable commands during program/erase suspend after tpsl/tesl" (e.g. fast read). refer to "table 19. ac characteristics" for tpsl and tesl timings. "table 11. acceptable commands during suspend (tpsl/tesl not required)" lists the commands for which the tpsl and tesl latencies do not apply. for example, rdsr, rdscur, rsten, and rst can be issued at any time after the suspend instruction. security register bit 2 (psb) and bit 3 (esb) can be read to check the suspend status. the psb (program suspend bit) sets to 1 when a program operation is suspended. the esb (erase suspend bit) sets to 1 when an erase operation is suspended. the psb or esb clears to 0 when the program or erase operation is resumed. table 10. acceptable commands during program/erase suspend after tpsl/tesl command name command code suspend type program suspend erase suspend read 03h ? ? fast read 0bh ? ? dread 3bh ? ? qread 6bh ? ? 2read bbh ? ? 4read ebh ? ? rdsfdp 5ah ? ? rdid 9fh ? ? rems 90h ? ? sbl c0 ? ? enso b1h ? ? exso c1h ? ? wren 06h ? resume 7ah or 30h ? ? pp 02h ? 4pp 38h ? advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
57 table 11. acceptable commands during suspend (tpsl/tesl not required) command name command code suspend type program suspend erase suspend wrdi 04h ? ? rdsr 05h ? ? rdcr 15h ? ? rdscur 2bh ? ? res abh ? ? rsten 66h ? ? rst 99h ? ? nop 00h ? ? figure 33. suspend to read/program latency cs# tpsl / tesl suspend command read/program command tpsl: program latency tesl: erase latency notes: 1. please note that program only available after the erase-suspend operation 2. to check suspend ready information, please read security register bit2(psb) and bit3(esb) figure 34. resume to suspend latency cs# tprs: program resume to another suspend ters: erase resume to another suspend resume command suspend command tprs / ters advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
58 figure 35. resume to read latency cs# tse / tbe / tpp resume command read command 9-30-1. erase suspend to program the erase suspend to program feature allows page programming while an erase operation is suspended. page programming is permitted in any unprotected memory except within the sector of a suspended sector erase operation or within the block of a suspended block erase operation. the write enable (wren) instruction must be issued before any page program instruction. a page program operation initiated within a suspended erase cannot itself be suspended and must be allowed to fnish before the suspended erase can be resumed. the status register can be polled to determine the status of the page program operation. the wel and wip bits of the status register will remain 1 while the page program operation is in progress and will both clear to 0 when the page program operation completes. 9-31. program resume and erase resume the resume instruction resumes a suspended page program, sector erase, or block erase operation. before issuing the resume instruction to restart a suspended erase operation, make sure that there is no page program operation in progress. immediately after the serial fash receives the resume instruction, the wel and wip bits are set to 1 and the psb or esb is cleared to 0. the program or erase operation will continue until fnished ( "figure 35. resume to read latency" ) or until another suspend instruction is received. a resume-to-suspend latency of tprs or ters must be observed before issuing another suspend instruction ( "figure 34. resume to suspend latency" ). please note that the resume instruction will be ignored if the serial fash is in performance enhance mode. make sure the serial fash is not in performance enhance mode before issuing the resume instruction. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
59 9-32. no operation (nop) the "no operation" command is only able to terminate the reset enable (rsten) command and will not affect any other command. the sio[3:1] are don't care. 9-33. software reset (reset-enable (rsten) and reset (rst)) the software reset operation combines two instructions: reset-enable (rsten) command and reset (rst) command. it returns the device to a standby mode. all the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. to execute reset command (rst), the reset-enable (rsten) command must be executed frst to perform the reset operation. if there is any other command to interrupt after the reset-enable command, the reset-enable will be invalid. the sio[3:1] are "don't care". if the reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. the reset time is different depending on the last operation. longer latency time is required to recover from a program operation than from other operations. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
60 figure 36. software reset recovery figure 37. reset sequence cs# sclk sio0 66h mode 3 mode 0 mode 3 mode 0 99h command command tshsl 9-34. high voltage operation the fash device supports high voltage operation. this opeartion allows user can have better performance in following operations: program/erase operation. to enable high voltage opeartion, wp#/sio2 need to apply vhv during whole operation. if the voltage can not sustain in vhv range, the program/erase opeation might be failed. cs# mode 66 99 stand-by mode tready2 note: refer to "table 15-2. reset timing-(other operation)" for tready2 data. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
61 9-35. read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is same as fast_read: cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a jedec standard, jesd216. figure 38. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
62 table 12. signature and parameter identifcation data values description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers this number is 0-based. therefore, 0 indicates 1 parameter header. 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number (macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh sfdp table below is for MX25R1035Fm1il0, MX25R1035Fm2il0, MX25R1035Fznil0 and MX25R1035Fzuil0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
63 table 13. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction required for writing to volatile status registers 0: not required 1: required 00h to be written to the status register 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 1b f1h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support 1=support 19 0b (1-2-2) fast read 0=not support 1=support 20 1b (1-4-4) fast read 0=not support 1=support 21 1b (1-1-4) fast read 0=not support 1=support 22 1b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 000f ffffh (1-4-4) fast read number of wait states (note3) 0 0000b: not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 38h 04:00 0 0100b 44h (1-4-4) fast read number of mode bits (note4) mode bits: 000b: not supported; 010b: 2 bits 07:05 010b (1-4-4) fast read opcode 39h 15:08 ebh ebh (1-1-4) fast read number of wait states 0 0000b: not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 3ah 20:16 0 1000b 08h (1-1-4) fast read number of mode bits mode bits: 000b: not supported; 010b: 2 bits 23:21 000b (1-1-4) fast read opcode 3bh 31:24 6bh 6bh sfdp table below is for MX25R1035Fm1il0, MX25R1035Fm2il0, MX25R1035Fznil0 and MX25R1035Fzuil0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
64 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) (1-1-2) fast read number of wait states 0 0000b: not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 3ch 04:00 0 1000b 08h (1-1-2) fast read number of mode bits mode bits: 000b: not supported; 010b: 2 bits 07:05 000b (1-1-2) fast read opcode 3dh 15:08 3bh 3bh (1-2-2) fast read number of wait states 0 0000b: not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 3eh 20:16 0 0100b 04h (1-2-2) fast read number of mode bits mode bits: 000b: not supported; 010b: 2 bits 23:21 000b (1-2-2) fast read opcode 3fh 31:24 bbh bbh (2-2-2) fast read 0=not support 1=support 40h 00 0b eeh unused 03:01 111b (4-4-4) fast read 0=not support 1=support 04 0b unused 07:05 111b unused 43h:41h 31:08 ffh ffh unused 45h:44h 15:00 ffh ffh (2-2-2) fast read number of wait states 0 0000b: not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 46h 20:16 0 0000b 00h (2-2-2) fast read number of mode bits mode bits: 000b: not supported; 010b: 2 bits 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 ffh ffh (4-4-4) fast read number of wait states 0 0000b: not supported; 0 0100b: 4 0 0110b: 6; 0 1000b: 8 4ah 20:16 0 0000b 00h (4-4-4) fast read number of mode bits mode bits: 000b: not supported; 010b: 2 bits 23:21 000b (4-4-4) fast read opcode 4bh 31:24 ffh ffh sector type 1 size sector/block size = 2^n bytes (note5) 0ch: 4kb; 0fh: 32kb; 10h: 64kb 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 00h: n/a; 0fh: 32kb; 10h: 64kb 4eh 23:16 0fh 0fh sector type 2 erase opcode 4fh 31:24 52h 52h sector type 3 size sector/block size = 2^n bytes 00h: n/a; 0fh: 32kb; 10h: 64kb 50h 07:00 10h 10h sector type 3 erase opcode 51h 15:08 d8h d8h sector type 4 size 00h: n/a, this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh sfdp table below is for MX25R1035Fm1il0, MX25R1035Fm2il0, MX25R1035Fznil0 and MX25R1035Fzuil0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
65 table 14. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 36h 00h 36h vcc supply minimum voltage 1650h=1.650v, 1750h=1.750v 2250h=2.250v, 2300h=2.300v 2350h=2.350v, 2650h=2.650v 2700h=2.700v 63h:62h 23:16 31:24 00h 17h 00h 17h h/w reset# pin 0=not support 1=support 65h:64h 00 1b f99dh h/w hold# pin 0=not support 1=support 01 0b deep power down mode 0=not support 1=support 02 1b s/w reset 0=not support 1=support 03 1b s/w reset opcode reset enable (66h) should be issued before reset opcode 11:04 1001 1001b (99h) program suspend/resume 0=not support 1=support 12 1b erase suspend/resume 0=not support 1=support 13 1b unused 14 1b wrap-around read mode 0=not support 1=support 15 1b wrap-around read mode opcode 66h 23:16 c0h c0h wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 64h 64h individual block lock 0=not support 1=support 6bh:68h 00 0b cffeh individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 1b individual block lock opcode 09:02 1111 1111b (ffh) individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 1b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11b unused 31:16 ffh ffh unused 6fh:6ch 31:00 ffh ffh MX25R1035Fm1il0-sfdp_2015-01-05,sf10 sfdp table below is for MX25R1035Fm1il0, MX25R1035Fm2il0, MX25R1035Fznil0 and MX25R1035Fzuil0 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
66 note 1: h/b is hexadecimal or binary. note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: wait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch,32kb=2^0fh,64kb=2^10h not e 6: all unused and undefined area data is blank ffh for sfdp tables that are defined in parameter identifcation header. all other areas beyond defned sfdp table are reserved by macronix. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
67 10. reset driving the reset# pin low for a period of trlrh or longer will reset the device. after reset cycle, the device is at the following states: - standby mode - all the volatile bits such as wel/wip/sram lock bit will return to the default status as power on. if the device is under programming or erasing, driving the rese t# pin low will also terminate the operation and data could be lost. during the resetting cycle, the so data becomes high impedance and the current will be reduced to minimum. figure 39. reset timing trhsl trs trh trlrh tready1 / tready2 sclk reset# cs# symbol parameter min. typ. max. unit trhsl reset# high before cs# low 10 us trs reset# setup time 15 ns trh reset# hold time 15 ns trlrh reset# low pulse width 10 us tready1 reset recovery time 35 us table 15-1. reset timing-(power on) symbol parameter min. typ. max. unit trhsl reset# high before cs# low 10 us trs reset# setup time 15 ns trh reset# hold time 15 ns trlrh reset# low pulse width 10 us tready2 reset recovery time (during instruction decoding) 40 us reset recovery time (for read operation) 35 us reset recovery time (for program operation) 310 us reset recovery time(for se4kb operation) 12 ms reset recovery time (for be32k/64k operation) 25 ms reset recovery time (for chip erase operation) 100 ms reset recovery time (for wrsr operation) 40 ms table 15-2. reset timing-(other operation) advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
68 11. power-on state the device is at the following states when power-up: - standby mode (please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage until the vcc reaches the following levels: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. when vcc is lower than vwi (por threshold voltage value), the internal logic is reset and the fash device has no response to any command. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the "figure 46. power-up timing" . note: - t o stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uf) - a t power-down stage, the vcc drops below vwi level, all operations are disable and device has no response to any command. the data corruption might occur during this stage if a write, program, erase cycle is in progress. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
69 12. electrical specifications figure 40. maximum negative overshoot waveform figure 41. maximum positive overshoot waveform 0v -1.0v 20ns vcc+1.0v vcc 20ns notice: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v or -1.0v for period up to 20ns. table 16. absolute maximum ratings rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 4.0v table 17. capacitance ta = 25c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
70 figure 42. input test waveforms and measurement level figure 43. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf/15pf including jig capacitance advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
71 table 18. dc characteristics notes : 1. typical values at vcc = 3.0v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 8 18 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 0.2 0.5 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 6 ma f=16mhz (4x i/o) sclk=0.1vcc/0.9vcc, so=open 4 ma f=33mhz sclk=0.1vcc/0.9vcc, so=open 4 ma f=16mhz (2x i/o) sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 4 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 4 ma program status register in progress, cs#=vcc icc4 vcc sector/block (64k) erase current (se/be) 1 4 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 4 ma erase in progress, cs#=vcc vhv high voltage applied at wp# pin 7 8 v test condition, vcc=2.0v vil input low voltage -0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage 0.2 v iol = 100ua voh output high voltage vcc-0.2 v ioh = -100ua low power mode (confguration register-2 bit1= 0): advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
72 notes : 1. typical values at vcc = 3.0v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd iwph leakage current while wp# at vhv 30 ua vcc < 2.1v isb1 vcc standby current 1 10 50 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 0.2 0.5 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 8 ma f=80mhz sclk=0.1vcc/0.9vcc, so=open 12 ma f=80mhz (2x i/o) sclk=0.1vcc/0.9vcc, so=open 10 ma f=33mhz (4x i/o) sclk=0.1vcc/0.9vcc, so=open 9 13 ma f=80mhz (4x i/o) sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 10 15 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 10 15 ma program status register in progress, cs#=vcc icc4 vcc sector/block (64k) erase current (se/be) 1 10 15 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 10 15 ma erase in progress, cs#=vcc vhv high voltage applied at wp# pin 7 8 v test condition, vcc=2.0v vil input low voltage -0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage 0.2 v iol = 100ua voh output high voltage vcc-0.2 v ioh = -100ua high performance mode (confguration register-2 bit1= 1): advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
73 table 19. ac characteristics symbol alt. parameter min. typ. (2) max. unit fsclk fc clock frequency for the following instructions: fast_read, rdsfdp, pp, se, be32k, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr (8) d.c. 33 mhz frsclk fr clock frequency for read instructions 33 mhz ftsclk ft clock frequency for 2read/dread instructions 16 mhz fq clock frequency for 4read/qread instructions 16 mhz f4pp clock frequency for 4pp (quad page program) 33 mhz tch (1) tclh clock high time others (fsclk) 45% x (1/fsclk) ns normal read (frsclk) 13 ns tcl (1) tcll clock low time others (fsclk) 45% x (1/fsclk) ns normal read (frsclk) 13 ns tclch (10) clock rise time (peak to peak) 0.1 v/ns tchcl (10) clock fall time (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 3 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl tcsh cs# deselect time read 15 ns write/erase/program 30 ns tshqz (10) tdis output disable time 8 ns tclqv tv clock low to output valid loading: 30pf/15pf loading: 30pf 12 ns loading: 15pf 10 ns tclqx tho output hold time 0 ns twhsl (3) write protect setup time 10 ns tshwl (3) write protect hold time 10 ns tdp cs# high to deep power-down mode 10 us tdpdd delay time for release from deep power-down mode once entering deep power-down mode 30 us tcrdp cs# toggling time before release from deep power-down mode 20 ns trdp recovery time for release from deep power down mode 35 us tres2 cs# high to standby mode with electronic signature read 30 us tw write status register cycle time 40 ms twms write status register cycle time for mode switching 20 us tesl (9) erase suspend latency 60 us tpsl (9) program suspend latency 60 us tprs (4) latency between program resume and next suspend 0.3 100 us ters (5) latency between erase resume and next suspend 0.3 400 us low power mode (confguration register-2 bit1= 0): advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
74 symbol alt. parameter min. typ. (2) max. unit tbp byte-program 50 125 us byte-program (applied vhv at wp# pin) 40 100 us tpp page program cycle time 4 8 ms page program cycle time (applied vhv at wp# pin) 0.6 1.2 ms tse sector erase cycle time 100 300 ms sector erase cycle time (applied vhv at wp# pin) 70 210 ms tbe32k block erase (32kb) cycle time 0.5 1.5 s block erase (32kb) cycle time (applied vhv at wp# pin) 0.35 1.0 s tbe block erase (64kb) cycle time 1 3 s block erase (64kb) cycle time (applied vhv at wp# pin) 0.7 2.1 s tce chip erase cycle time 3.125 9.375 s chip erase cycle time (applied vhv at wp# pin) 0.875 2.625 s low power mode - continued: advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
75 symbol alt. parameter min. typ. (2) max. unit fsclk fc clock frequency for the following instructions: fast_read, rdsfdp, pp, se, be32k, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr (8) d.c. 80 mhz frsclk fr clock frequency for read instructions 33 mhz ftsclk ft clock frequency for 2read/dread instructions 80 mhz fq clock frequency for 4read/qread instructions 80 mhz f4pp clock frequency for 4pp (quad page program) 80 mhz tch (1) tclh clock high time others (fsclk) 45% x (1/fsclk) ns normal read (frsclk) 13 ns tcl (1) tcll clock low time others (fsclk) 45% x (1/fsclk) ns normal read (frsclk) 13 ns tclch (10) clock rise time (peak to peak) 0.1 v/ns tchcl (10) clock fall time (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 3 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl tcsh cs# deselect time read 15 ns write/erase/program 30 ns tshqz (10) tdis output disable time 8 ns tclqv tv clock low to output valid loading: 30pf/15pf loading: 30pf 8 ns loading: 15pf 6 ns tclqx tho output hold time 0 ns twhsl (3) write protect setup time 10 ns tshwl (3) write protect hold time 10 ns tdp cs# high to deep power-down mode 10 us tdpdd delay time for release from deep power-down mode once entering deep power-down mode 30 us tcrdp cs# toggling time before release from deep power- down mode 20 ns trdp recovery time for release from deep power down mode 35 us tres2 cs# high to standby mode with electronic signature read 30 us tw write status register cycle time 40 ms write status register cycle time (applied vhv at wp# pin) 40 ms twms write status register cycle time for mode switching 20 us tesl (9) erase suspend latency 40 us tpsl (9) program suspend latency 40 us tprs (4) latency between program resume and next suspend 0.3 100 us ters (5) latency between erase resume and next suspend 0.3 400 us high performance mode (confguration register-2 bit1= 1): advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
76 notes: 1. tch + tcl must be greater than or equal to 1/ frequency. 2. typical values given for ta=25 c. not 100% tested. 3. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 4. for tprs, min. time is needed to issue next program suspend command. however, a period of time equal to/or longer than typ. timing is also required to complete the program progress. 5. for tres, min. timing is needed to issue next erase suspend command. however, a period of time equal to/or longer than typ. timing is also required to complete the erase progress. 6. if the address range is within 4mb, the 4read/qread clock rate could achieve to 16mhz for 4read/qread operation. if user wants to keep 4read/qread at 16mhz for address range that is more than 4mb, it is necessary to re-issue 4read/qread command again after each 4mb boundary. 7. test condition is shown as "figure 42. input test waveforms and measurement level", "figure 43. output loading" . 8. wrsr speed max. is 33mhz when issuing wrsr for performance mode switch no matter high performance mode to low power mode or low power mode to high performance mode. 9. latency time is required to complete erase/program suspend operation until wip bit is "0". 10. the value guaranteed by characterization, not 100% tested in production. symbol alt. parameter min. typ. (2) max. unit tbp byte-program 40 100 us byte-program (applied vhv at wp# pin) 40 100 us tpp page program cycle time 1.2 2.4 ms page program cycle time (applied vhv at wp# pin) 0.6 1.2 ms tse sector erase cycle time 80 240 ms sector erase cycle time (applied vhv at wp# pin) 70 210 ms tbe32k block erase (32kb) cycle time 0.4 1.2 s block erase (32kb) cycle time (applied vhv at wp# pin) 0.35 1.0 s tbe block erase (64kb) cycle time 0.8 2.4 s block erase (64kb) cycle time (applied vhv at wp# pin) 0.7 2.1 s tce chip erase cycle time 1.25 3.75 s chip erase cycle time (applied vhv at wp# pin) 0.875 2.625 s high performance mode - continued: advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
77 notes : 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "table 19. ac characteristics" . symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v 13. operating conditions at device power-up and power-down ac timing illustrated in "figure 44. ac timing at device power-up" and "figure 45. power-down sequence" are for the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ignored, the device will not operate correctly. during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 44. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
78 figure 45. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. figure 46. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) v wi note: vcc (max.) is 3.6v and vcc (min.) is 1.7v. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
79 13-1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). figure 47. power up/down and voltage drop table 20. power-up/down voltage and timing vcc time vcc (max.) vcc (min.) v tpwd tvsl chip select is not allowed full device access allowed pwd (max.) for power-down to power-up operation, the vcc of fash device must below v pwd for at least tpwd timing. please check the table below for more detail. note: these parameters are characterized only. symbol parameter min. max. unit tvsl vcc(min.) to device operation 800 us vwi write inhibit voltage 1.1 1.5 v v pwd vcc voltage needed to below v pwd for ensuring initialization will occur deep power mode 0.4 v others 0.9 v tpwd the minimum duration for ensuring initialization will occur 300 us tvr vcc rise time 20 500000 us/v vcc vcc power supply 1.7 3.6 v advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
80 14. erase and programming performance notes: 1. typical erase assumes the following conditions: 25 c, 3.0v , and all zero pattern. 2. under worst conditions of 85 c and 1.7v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming command. 4. typical program assumes the following conditions: 25 c, 3.0v , and checkerboard pattern. parameter min. typ. (1) max. (2) unit write status register cycle time 40 ms sector erase cycle time (4kb) 100 300 ms sector erase cycle time (4kb) (applied vhv at wp# pin) 70 210 ms block erase cycle time (32kb) 0.5 1.5 s block erase cycle time (32kb) (applied vhv at wp# pin) 0.35 1.0 s block erase cycle time (64kb) 1 3 s block erase cycle time (64kb) (applied vhv at wp# pin) 0.7 2.1 s chip erase cycle time 3.125 9.375 s chip erase cycle time (applied vhv at wp# pin) 0.875 2.625 s byte program time 50 (4) 125 us byte program time (applied vhv at wp# pin) 40 100 us page program time 4 (4) 8 ms page program time (applied vhv at wp# pin) 0.6 1.2 ms erase/program cycle 100,000 cycles low power mode (confguration register-2 bit1= 0): parameter min. typ. (1) max. (2) unit write status register cycle time 40 ms write status register cycle time (applied vhv at wp# pin) 40 ms sector erase cycle time (4kb) 80 240 ms sector erase cycle time (4kb) (applied vhv at wp# pin) 70 210 ms block erase cycle time (32kb) 0.4 1.2 s block erase cycle time (32kb) (applied vhv at wp# pin) 0.35 1.0 s block erase cycle time (64kb) 0.8 2.4 s block erase cycle time (64kb) (applied vhv at wp# pin) 0.7 2.1 s chip erase cycle time 1.25 3.75 s chip erase cycle time (applied vhv at wp# pin) 0.875 2.625 s byte program time 40 (4) 100 us byte program time (applied vhv at wp# pin) 40 100 us page program time 1.2 (4) 2.4 ms page program time (applied vhv at wp# pin) 0.6 1.2 ms erase/program cycle 100,000 cycles high performance mode (confguration register-2 bit1= 1): advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
81 15. latch-up characteristics min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 1.8v, one pin at a time. advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
82 16. ordering information part no. clock (mhz) temperature package remark MX25R1035Fm1il0 80 -40 c~85 c 8-sop (150mil) MX25R1035Fm2il0 80 -40 c~85 c 8-sop (200mil) MX25R1035Fzuil0 80 -40 c~85 c 8-uson (2x3mm) advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
83 17. part name description mx 25 r l0 m2 i option: l0: with low power mode temperature range: i: industrial (-40c to 85c) package: m1: 8-sop(150mil) m2: 8-sop(200mil) zu: 8-uson (2x3mm) density & mode: 1035f: 1mb type: r: wide vcc range (1.7v~3.6v) device: 25: serial flash 1035f advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
84 18. package information advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
85 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
86 advanced information rev. 0.00, jan. 12, 2015 MX25R1035F p/n: pm2218
MX25R1035F 87 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which have been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2015. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only. for the contact and order information, please visit macronixs web site at: http://www.macronix.com

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